In comparison to other types of metal oxide semiconductor field effect transistors (MOSFETs), Silicon carbide MOSFETs excel in a number of ways, including switching speed, operating temperature, breakdown voltage, and linear current-voltage characteristics.
What is holding back the widespread adoption of silicon carbide?
In addition to the immaturity of the SiC material, the irregularity of the device parameters, and the rapid switching speed, current imbalance among the paralleled SiC MOSFETs has been a practical difficulty for the use of SiC MOSFETs in high current applications.
Due to mismatched circuit parameters or differences in semiconductor fabrication, the current of paralleled power semiconductor devices may be unbalanced, leading to accelerated degradation and long-term reliability issues.
Numerous efforts have been devoted to analyzing and resolving the current imbalance problem associated with paralleling SiC devices. A comprehensive analysis of existing solutions is discussed in detail.
Approaches for Mitigating Current Imbalance
Either passive or active approaches can address the current mismatch between paralleled devices, as shown in Fig. 1. To lessen the effects of electrical parameter mismatches between loops, passive techniques can optimize the package/circuit layout or preselect the chips.
Fig. 1. Approaches for Mitigating Current Imbalance/
Active methods make use of auxiliary circuits or components to achieve current balance. Both passive and active external components are included. By incorporating passive components into the gate loop or power loop, methods that rely on external passive components can modify the current distribution.
To dynamically alter the device's features on a cycle-by-cycle basis, approaches involving external active components often utilize adjustable gate driver solutions.
Advantages of Passive Method
In general, passive methods are inexpensive and don't require a separate component. Manufacturers prefer it because it can be used during fabrication.
The commercially available power modules are getting closer to optimum switches by continuously enhancing the die screening technique and optimizing package layout.
The power module can still be improved, but there are several technical and financial obstacles to overcome.
Concept of ‘Known Good Die’
SiC MOSFETs frequently employ the idea of a known good die (KGD), which implies that the important device parameters may be known.
This helps the die screening method, which is used in multichip power modules, increase the efficiency of current sharing across the paralleled devices.
Challenges
But there are still some difficulties. The device must first select one parameter or an algorithm from among the several device parameters to perform die binning or screening.
To decrease the tolerance of the device parameters, SiC suppliers are now working to improve the device process maturity. On the other side, a workable die-binning technique is also being developed and estimated.
The KGD idea is still predicated on room temperature, which is a second issue. Considering high-temperature metallization oxidation, cost, efficiency, etc., high-temperature KGD for mass production is still fairly difficult.
A more efficient and intelligent die binning or sorting mechanism for SiC power devices is required for the multichip SiC power module packaging. The sorting or binning shouldn't be done based on a single device parameter.
It is necessary to create a comprehensive device parameter that captures all aspects of a device's performance, including paralleling performance, robustness, dependability, and cost.
In addition, efficient burn-in test equipment and high-temperature, low-cost KGD measurement tools are anticipated for the collection of high-temperature device data.
Future Trends
The manufacturing industry is incorporating artificial intelligence (AI) algorithms more and more, which makes design smarter. All SiC dies are examined before packing in order to determine their electrical properties, which enables the implementation of preselection.
A number of computer-aided automatic layout generation techniques that attempt to reduce the parasitic inductance in the current loop were developed. The evolution of power semiconductor device manufacturing will follow a future trend that involves more AI in layout design.
Advantages of Active Methods
When passive procedures are no longer effective, active methods are typically used as backup plans. For example, paralleled discrete devices are frequently used in electric vehicles since they are more affordable than power modules. Active techniques can be used in these circumstances to increase the system's long-term dependability.
Challenges
The first is that including external passive components might raise the price and add extra parasitics to the loop, which can cause crosstalk noise, voltage overshoot, or false triggering.
Second, SiC mosfet switching transients, which are typically within 100 ns, make the active gate driver an immature technology. A SiC module's di/dt can reach 5 A/ns. It is typically difficult to detect the current, interpret the signal, and time the sequence in such a brief period of time.
To modify the switching slew rate, for instance, a variable driver voltage active gate driver typically modifies the driver voltage during the Miller plateau. It is challenging to identify the Miller plateau and determine the best driver voltage for it.
To reduce the overshoot voltage, it uses an exclusive augmented turn-off driver voltage profile. However, each SiC MOSFET turn-off procedure is optimized via software settings.
Research on closed-loop control for AGD in academia has focused on the Rogowski coil, the voltage on the stray inductance, and the current transformer.
Active Gate Driver Method
An efficient, low-cost device current measuring method, or an equivalent device current acquisition approach, is required for precise device current distribution optimization using the active gate driver method.
The TESP technique for estimating the junction temperature could be useful in the active gate driver method. Typically, the goal is to regulate the steady-state or dynamic current distribution so as to restrict the junction temperature differences.
Therefore, using junction temperature estimation for each device, AGD may modify the switching speed or the effective thermal time constant.
Rdson adjustments can be used to address static current imbalances. The only variable parameter is the typical turn-ON driver voltage because gate threshold voltage and other parameters are all decided upon during die production.
Consequently, a variable static driver voltage is required to alter the static current distribution. Since Rdson is important to junction temperature that is significantly impacted by load current, it is preferable to have a turn-on driver voltage that changes cycle by cycle.
To correct the static current imbalance in paralleled MOSFETs, various turn-on driver voltage levels are applied to each MOSFET. Utilizing a buck converter and an adjustable power supply allows for the implementation of turn-on driver voltage adjustment.
Summarizing the Key Points
- SiC MOSFETs offer advantages over other types of MOSFETs, including higher efficiency and faster switching speeds.
- However, there are challenges to their widespread adoption, such as high cost and limited availability.
- One major challenge in using paralleled SiC devices is current imbalance, which can lead to accelerated degradation and reliability issues.
- Both passive and active approaches can be used to mitigate current imbalances, such as optimizing package/circuit layout or using supplementary circuits/components.
- Active approaches may involve adjustable gate drivers or external active components to dynamically alter device features on a cycle-by-cycle basis.
Reference
Li, Helong, Shuang Zhao, Xiongfei Wang, Lijian Ding, and Homer Alan Mantooth. “Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions.” IEEE Transactions on Power Electronics 38, no. 8 (August 2023): 9731–49. https://doi.org/10.1109/tpel.2023.3278270.
