What is CLOCK GENERATOR? What does CLOCK GENERATOR mean? CLOCK GENERATOR meaning & explanation
IC CLK BUFFER PLL 64QFN
The SI5347 is a high-performance, jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. Furthermore, Huge range of Semiconductors, Capacitors, Resistors and IcS in stock. Welcome RFQ.
The following figure is the diagram of SI5347 Pinout.
Pinout
The following figure is the diagram of SI5347 Footprint.
Footprint
The SI5347 is a high-performance, jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5347 is easy with Silicon Labs' ClockBuilder Pro™ software. Factory preprogrammed devices are also available.
This article will introduce SI5347 systematically from its features, pinout to its specifications, applications, also including SI5347 datasheet and so much more.
● Four or two DSPLLs to synchronize to multiple inputs
● Generates any combination of output frequencies from any input frequency
● Ultra low jitter:
◆ 95 fs typ (12 kHz – 20 MHz)
● Input frequency range:
◆ Differential: 8 kHz to 750 MHz
◆ LVCMOS: 8 kHz to 250 MHz
● Output frequency range:
◆ Differential: up to 720 MHz
◆ LVCMOS: up to 250 MHz
● Flexible crosspoints route any input to any output clock
● Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz
● Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude
● Status monitoring (LOS, OOF, LOL)
● Hitless input clock switching: automatic or manual
● Locks to gapped clock inputs
● Automatic free-run and holdover modes
● Fastlock feature for low nominal bandwidths
● Glitchless on-the-fly DSPLL frequency changes
● DCO mode: as low as 0.01 ppb steps per DSPLL
● Core voltage:
◆ VDD: 1.8 V ±5%
◆ VDDA: 3.3 V ±5%
● Independent output clock supply pins: 3.3, 2.5, or 1.8 V
● Output-output skew:
◆ Using same DSPLL: 65 ps (Max)
● Serial interface: I2C or SPI
● In-circuit programmable with non-volatile OTP memory
● ClockBuilder Pro software simplifies device configuration
● Si5347: Quad DSPLL, 64-QFN 9×9 mm
● Temperature range: –40 to +85 °C
● Pb-free, RoHS-6 compliant
Silicon Labs SI5347B-B-GM technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI5347B-B-GM.
| Attribute | Value |
|---|---|
| Factory Lead Time | 6 Weeks |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 64-VFQFN Exposed Pad |
| Frequency(Max) | 350MHz |
| Operating Temperature | -40°C~85°C |
| Packaging | Tray |
| Published | 1997 |
| Part Status | Not For New Designs |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 64 |
| ECCN Code | EAR99 |
| Additional Feature | ALSO REQUIRES 3.3V SUPPLY |
| Voltage - Supply | 1.71V~3.47V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Attribute | Value |
|---|---|
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Output | CML, HCSL, LVCMOS, LVDS, LVPECL |
| JESD-30 Code | S-XQCC-N64 |
| Qualification Status | Not Qualified |
| Number of Circuits | 1 |
| uPs/uCs/Peripheral ICs Type | CLOCK GENERATOR, PROCESSOR SPECIFIC |
| Supply Current-Max | 240mA |
| Input | LVCMOS, LVDS, LVPECL, Crystal |
| Ratio - Input:Output | 5:8 |
| Primary Clock/Crystal Frequency-Nom | 54MHz |
| PLL | Yes |
| Differential - Input:Output | Yes/Yes |
| Divider/Multiplier | Yes/No |
| Length | 9mm |
| Height Seated (Max) | 0.9mm |
| Width | 9mm |
| RoHS Status | RoHS Compliant |
The following is the Block Diagram of SI5347.
Si5347 Block Diagram
| Model number | Manufacturer | Description |
| SI5347B-A-GM | Silicon Laboratories Inc | Processor Specific Clock Generator, 350MHz, CMOS, 9 X 9 MM, ROHS COMPLIANT, MO-220, QFN-64 |
| SI5347B-A-GMR | Silicon Laboratories Inc | Processor Specific Clock Generator, 350MHz, CMOS, 9 X 9 MM, ROHS COMPLIANT, MO-220, QFN-64 |
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● Broadcast video
The following diagrams show the SI5347 Package.
View A
View B
The following diagram shows the SI5347 Package PCB Land Pattern.
PCB Land Pattern
The following is the Top Marking of SI5347.
Top Marking
Silicon Labs (NASDAQ: SLAB) is a leading provider of silicon, software and system solutions for the Internet of Things, Internet infrastructure, industrial control, consumer and automotive markets. Resolving the electronics industry's toughest problems, providing customers with significant advantages in performance, energy savings, connectivity, and design simplicity. Backed by world-class engineering teams with unsurpassed software and mixed-signal design expertise, Silicon Labs empowers developers with the tools and technologies they need to advance quickly and easily from initial idea to final product.
Download datasheets and manufacturer documentation for Silicon Labs SI5347B-B-GM.
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